The present disclosure relates to semiconductor devices and, more particularly, to MOS transistors and their methods of fabrication with well or substrate body bias provisions electrically connected to one of a transistor's source/drain regions.
A semiconductor integrated circuit may comprise a plurality of NMOS transistors on P-type well(s) and PMOS transistor on N-type well(s). Generally, the semiconductor integrated circuit may comprise provisions for grounding or applying a voltage to the N-type well(s) or the P-type well(s). For conventional devices, the transistors are formed on active regions of the wells, which may extend to regions separate and beyond the fabricated transistors to receive well or substrate body biasing. For some conventional devices, a plurality of transistors may be formed on a single well, which likewise may receive well biasing at region(s) separate from the plurality of transistors.
Referring to FIG. 1, a conventional semiconductor device may comprise device isolation layer 12 disposed in a predetermined region of a semiconductor substrate. The device isolation layer 12 may comprise an outline that defines first and second active regions in respective N-type and P-type regions 10a, 10b of the substrate. A PMOS transistor may be formed on the first active region of N-type region 10a between sidewalls 13a of isolation layer 12. Likewise, an NMOS transistor may be formed on the second active region of the P-type region 10b between sidewalls 13b of isolation layer 12.
The PMOS transistor may comprise first gate pattern 14a crossing the first active region. P-type source/drain regions 16a of the PMOS transistor may be formed in the first active region on opposite sides of first gate pattern 14a. The NMOS transistor may comprise second gate pattern 14b crossing the second active region. N-type source/drain regions 16b of the NMOS transistor may be formed in the second active region on opposite sides of the second gate pattern 14b. 
As shown in FIG. 1, such conventional semiconductor device may further comprise well bias regions 18a and 18b for enabling connection of respective N-well and P-well regions to receive respective well or substrate body biasings. Well bias regions 18a and 18b may be formed separate from their respective transistors but within the active regions of the transistors.
For highly integrated semiconductor devices, well bias regions may be formed at regular intervals in predetermined regions of the semiconductor substrate for a plurality of transistors and active regions. Referencing FIG. 2, such conventional semiconductor device 21 may comprise well bias regions 28 coupled at regular intervals to bias well 20B of the semiconductor substrate.
For this example, further referencing the conventional device of FIG. 2, device isolation layer 22 may be formed in a predetermined region of the semiconductor substrate 20 and with sidewalls 23 forming an outline to define a plurality of active regions. Transistors may be formed on the respective active regions. Each well bias region 28 which may be associated with a group of the plurality of the transistors may be coupled to a common well bias region 28. Unfortunately, however, the single common well bias region 28 of such conventional device, as shown in FIG. 2, may adversely affect an integrity of transistors 25 that may be more distant from well bias region 28. Such distant transistors may be more vulnerable to latch-up phenomenon or abnormal noise.